I wrote a behavioral verilog code for an unsigned 8.8 multiplier but when I simulate it, it doesn't show the right answer I would be happy if anybody can help! Module mult8(p,x,y).
8 to 1 Multiplexer HDL Verilog Code
This page of verilog sourcecode covers HDL code for 8 to 1 Multiplexer using verilog.
Symbol
Following is the symbol and truth table of 8 to 1 Multiplexer.
Truth Table
Verilog code
module mux8_1
input [7:0]I;
output [2:0]S;
output y;
input en;
reg y;
always @(en,S,I,y);
begin
if (en= =1)
begin
if (s= =000 y=I[0];
else if (s001) y=I[1];
else if (s001) y=I[2];
else if (s001) y=I[3];
else if (s001) y=I[4];
else if (s001) y=I[5];
else if (s001) y=I[6];
else if (s001) y=I[7];
end
else y=0;
end
end
end module
Simulation result
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8 To 1 Multiplexer Verilog
module mux_8_to_1_using_2_1(I,sel,Y);
input[7:0]I;
input[2:0]sel;
output Y;
wire[5:0]mux_out;
mux_2_to_1 M1(.i0(I[0]),.i1(I[1]),.sel(sel[0]),.out(mux_out[0]));
mux_2_to_1 M2(.i0(I[2]),.i1(I[3]),.sel(sel[0]),.out(mux_out[1]));
mux_2_to_1 M3(.i0(I[4]),.i1(I[5]),.sel(sel[0]),.out(mux_out[2]));
mux_2_to_1 M4(.i0(I[6]),.i1(I[7]),.sel(sel[0]),.out(mux_out[3]));
mux_2_to_1 M5(.i0(mux_out[0]),.i1(mux_out[1]),.sel(sel[1]),.out(mux_out[4]));
mux_2_to_1 M6(.i0(mux_out[2]),.i1(mux_out[3]),.sel(sel[1]),.out(mux_out[5]));
mux_2_to_1 M7(.i0(mux_out[4]),.i1(mux_out[5]),.sel(sel[2]),.out(Y));
endmodule
Verilog Code For 8 To 1 Multiplexer Using Structural Modelling
module mux_2_to_1(i0,i1,sel,out);
input i0,i1;
input sel;
output out;
assign out=sel?i1:i0;
endmodule